The present invention relates to a semiconductor memory including a ferroelectric capacitor and a method for driving the semiconductor memory.
A known semiconductor memory including a ferroelectric capacitor is composed of, as shown in FIG. 6, a field effect transistor (hereinafter referred to as the FET) 1 having a drain region 1a, a source region 1b and a gate electrode 1c, and a ferroelectric capacitor 2 having an upper electrode 2a, a lower electrode 2b and a ferroelectric film 2c. This semiconductor memory employs the non-destructive read-out system in which the lower electrode 2b of the ferroelectric capacitor 2 is connected to the gate electrode 1c of the FET 1, so as to use the ferroelectric capacitor 2 for controlling the gate potential of the FET 1. In FIG. 6, a reference numeral 3 denotes a substrate.
In writing a data in this semiconductor memory, a writing voltage is applied between the upper electrode 2a of the ferroelectric capacitor 2, which works as a control electrode, and the substrate 3.
For example, when a data is written by applying a voltage (control voltage) positive with respect to the substrate 3 to the upper electrode 2a, downward polarization is caused in the ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter, even when the upper electrode 2a is grounded, positive charge remains in the gate electrode 1c of the FET 1, and hence, the gate electrode 1c has a positive potential.
When the potential of the gate electrode 1c exceeds the threshold voltage of the FET 1, the FET 1 is in an on-state. Therefore, when a potential difference is caused between the drain region 1a and the source region 1b, a current flows between the drain region 1a and the source region 1b. Such a logical state of the ferroelectric memory for allowing a current to flow between the drain region 1a and the source region 1b is defined, for example, as xe2x80x9c1xe2x80x9d.
On the other hand, when a voltage negative with respect to the substrate 3 is applied to the upper electrode 2a of the ferroelectric capacitor 2, upward polarization is caused in the ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter, even when the upper electrode 2a is grounded, negative charge remains in the gate electrode 1c of the FET 1, and hence, the gate electrode 1c has a negative potential. In this case, the potential of the gate electrode 1c is always lower than the threshold voltage of the FET 1, the FET 1 is in an off-state. Therefore, even when a potential difference is caused between the drain region 1a and the source region 1b, no current flows between the drain region 1a and the source region 1b. Such a logical state of the ferroelectric memory for allowing no current to flow between the drain region 1a and the source region 1b is defined, for example, as xe2x80x9c0xe2x80x9d.
Even when the power supply to the ferroelectric capacitor 2 is shut off, namely, even when the voltage application to the upper electrode 2a of the ferroelectric capacitor 2 is stopped, the aforementioned logical states are retained, and thus, a nonvolatile memory is realized. Specifically, when power is supplied again to apply a voltage between the drain region 1a and the source region 1c after shutting off the power supply for a given period of time, a current flows between the drain region la and the source region 1b if the logical state is xe2x80x9c1xe2x80x9d, so that the data xe2x80x9c1xe2x80x9d can be read, and no current flows between the drain region 1a and the source region 1b if the logical state is xe2x80x9c0xe2x80x9d, so that the data xe2x80x9c0xe2x80x9d can be read.
In order to correctly retain a data while the power is being shut off (which characteristic for retaining a data is designated as retention), it is necessary to always keep the potential of the gate electrode 1c of the FET 1 to be higher than the threshold voltage of the FET 1 when the data is xe2x80x9c1xe2x80x9d and to always keep the potential of the gate electrode 1c of the FET 1 at a negative voltage when the data is xe2x80x9c0xe2x80x9d.
While the power is being shut off, the upper electrode 2a of the ferroelectric capacitor 2 and the substrate 3 have a ground potential, and hence, the potential of the gate electrode 1c is isolated. Therefore, ideally, as shown in FIG. 7, a first intersection c between a hysteresis loop 4 obtained in writing a data in the ferroelectric capacitor 2 and a gate capacitance load line 5 of the FET 1 obtained when a bias voltage is 0 V corresponds to the potential of the gate electrode 1c obtained in storing a data xe2x80x9c1xe2x80x9d, and a second intersection d between the hysteresis loop 4 and the gate capacitance load line 5 corresponds to the potential of the gate electrode 1c obtained in storing a data xe2x80x9c0xe2x80x9d. In FIG. 7, the ordinate indicates charge Q appearing in the upper electrode 2a (or the gate electrode 1c) and the abscissa indicates voltage V.
Actually, however, the ferroelectric capacitor 2 is not an ideal insulator but has a resistance component, and hence, the potential of the gate electrode 1c drops through the resistance component. This potential drop is exponential and has a time constant obtained by multiplying parallel combined capacitance of the gate capacitance of the FET 1 and the capacitance of the ferroelectric capacitor 2 by the resistance component of the ferroelectric capacitor 2. The time constant is approximately 104 seconds at most. Accordingly, the potential of the gate electrode 1c is halved within several hours.
Since the potential of the gate electrode 1c is approximately 1 V at the first intersection c as shown in FIG. 7, when the potential is halved, the potential of the gate electrode 1c becomes approximately 0.5 V, which is lower than the threshold voltage of the FET 1 (generally of approximately 0.7 V). As a result, the FET 1 that should be in an on-state is turned off in a short period of time.
In this manner, although the ferroelectric memory using the ferroelectric capacitor 2 for controlling the gate potential of the FET 1 has an advantage that a rewrite operation is not necessary after a data read operation, it has the following problem: The gate electrode 1c of the FET 1 obtains a potential after writing a data, and the ability for keeping the gate potential determines the retention characteristic. Since the time constant until discharge of the ferroelectric capacitor 2 is short due to the resistance component of the ferroelectric capacitor 2, the data retaining ability is short, namely, the retention characteristic is not good.
Furthermore, in accordance with increased integration and refinement of semiconductor integrated circuit devices, the area of a semiconductor memory built on a semiconductor integrated circuit device is desired to be reduced. In the conventional semiconductor memory, however, each memory cell includes the ferroelectric capacitor 2 and the FET 1 for reading a data stored in the ferroelectric capacitor 2, and hence, the area of each memory cell, namely, the area of the entire semiconductor memory, cannot be sufficiently reduced.
In consideration of the aforementioned conventional problems, a first object of the invention is improving the retention characteristic of a semiconductor memory including a ferroelectric capacitor for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a second object is reducing the area of the semiconductor memory.
The semiconductor memory of this invention comprises a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of the plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a selected ferroelectric capacitor selected from the plurality of ferroelectric capacitors; a set line connected to the other end of the plurality of successively connected ferroelectric capacitors; a bit line connected to a drain of the reading transistor at one end thereof; a reset line connected to a source of the reading transistor at one end thereof; and a plurality of word lines respectively corresponding to the plurality of ferroelectric capacitors and provided perpendicularly to the bit line for selecting the selected ferroelectric capacitor from the plurality of ferroelectric capacitors for data write or data read.
In the semiconductor memory of this invention, the gate of the reading transistor for detecting the displacement of the polarization of the ferroelectric film of the selected ferroelectric capacitor is connected to one end of the plural ferroelectric capacitors successively connected along the bit line direction. Therefore, there is no need to provide a reading transistor in every memory cell, and hence, not only the area of each memory cell but also the area of the entire semiconductor memory can be reduced.
Furthermore, since the plural word lines provided perpendicularly to the bit line are used for selecting a ferroelectric capacitor for data write or data read, even though merely one reading transistor is connected to the plural ferroelectric capacitors, the data write or data read can be definitely carried out in a selected ferroelectric capacitor.
Moreover, since the amplifying function of the reading transistor can be utilized in reading a data, the sensitivity for detecting the displacement of the polarization of the ferroelectric film of the selected ferroelectric capacitor can be improved.
The semiconductor memory of this invention preferably further comprises a plurality of selecting transistors respectively connected to the plurality of ferroelectric capacitors in parallel whose gates are respectively connected to the plurality of word lines.
In this manner, a ferroelectric capacitor for data write or data read can be selected by turning on/off the selecting transistors by controlling the voltages applied to the respective word lines. Also, a potential difference induced between the upper electrode and the lower electrode of the selected ferroelectric capacitor can be removed by turning on the selecting transistor, and hence, the lowering of the potential difference through a resistance component of the ferroelectric capacitor can be avoided, resulting in improving the retention characteristic.
In the semiconductor memory, it is preferred that a first division voltage obtained by dividing a reading voltage applied to the set line on the basis of a ratio between capacitance of the selected ferroelectric capacitor and gate capacitance of the reading transistor is induced to the gate of the reading transistor, and that the reading voltage is set to such magnitude that a relationship of VR greater than VT greater than VS holds among a threshold voltage VT of the reading transistor, a first division voltage VS induced to the gate of the reading transistor when a data is written in the selected ferroelectric capacitor and a first division voltage VR induced to the gate of the reading transistor when a data is not written in the selected ferroelectric capacitor.
When the reading voltage is set such magnitude that the relationship of VR greater than VT greater than VS holds, a data stored in a ferroelectric capacitor can be read without fail even if the potential difference induced between the upper electrode and the lower electrode of the ferroelectric capacitor is removed.
In the semiconductor memory, it is preferred that a second division voltage obtained by dividing a reading voltage applied to the set line on the basis of a ratio between capacitance of the selected ferroelectric capacitor and gate capacitance of the reading transistor is induced between an upper electrode and a lower electrode of the selected ferroelectric capacitor, and that the reading voltage is set to such magnitude that the second division voltage does not exceed a coercive voltage of the selected ferroelectric capacitor.
When the reading voltage is set to such magnitude that the second division voltage applied between the upper electrode and the lower electrode of the selected ferroelectric capacitor does not exceed the coercive voltage of the ferroelectric capacitor, the displacement of the polarization of the ferroelectric film can be definitely restored to that obtained before reading a data by removing the reading voltage applied to the set line.
The semiconductor memory preferably further comprises a load resistance connected, at one end thereof, to the other end of the bit line.
In this manner, voltage change caused at both ends of the load resistance owing to a current flowing between the drain and the source of the reading transistor, namely, flowing to the bit line, can be detected in applying the reading voltage to the set line. Therefore, a data written in the selected ferroelectric capacitor can be detected. Also, the voltage change caused in the load resistance can be always detected as far as the reading voltage is applied differently from voltage change caused in a load capacitor, and hence, the voltage change can be thus easily detected.
In the case where the semiconductor memory includes the load resistance, the load resistance is preferably a MOS transistor.
Thus, the load resistance can be actively driven.
In the case where the semiconductor memory includes the load resistance, it is preferred that a power voltage is applied to the other end of the load resistance, and that the semiconductor memory further comprises comparison means for comparing, with a reference voltage, voltage change caused at both ends of the load resistance owing to a current flowing between the drain and the source of the reading transistor in accordance with the displacement of the polarization of the ferroelectric film of the selected ferroelectric capacitor.
In this manner, by comparing, with the reference voltage, the voltage change caused at both ends of the load resistance owing to a current flowing between the drain and the source of the reading transistor, namely, a current flowing to the bit line, in applying the reading voltage to the set line, a data written in the selected ferroelectric capacitor can be easily and definitely detected.
The semiconductor memory of this invention preferably further comprises a second memory cell block having the same configuration as the memory cell block and disposed on a side of the memory cell block along a word line direction; a second bit line connected, at one end thereof, to a drain of a second reading transistor included in the second memory cell block; a first load resistance connected to the other end of the bit line at one end thereof and connected to a power voltage at the other end thereof; and a second load resistance connected to the other end of the second bit line at one end thereof and connected to the power voltage at the other end thereof, and it is preferred that the set line is connected to the other end of a plurality of ferroelectric capacitors included in the second memory cell block, that the reset line is connected to a source of the second reading transistor included in the second memory cell block, and that the semiconductor memory further comprises comparison means for comparing, in applying a reading voltage to the set line, first voltage change caused at both ends of the first load resistance owing to a current flowing between the drain and the source of the reading transistor with second voltage change caused at both ends of the second load resistance owing to a current flowing between the drain and the source of the second reading transistor.
In this manner, the first voltage change caused at both ends of the former load resistance owing to a current flowing between the drain and the source of the reading transistor included in the memory cell block where a data is read is compared with the second voltage change caused at both ends of the latter load resistance owing to a current flowing between the drain and the source of the second reading transistor included in the second memory cell block where a data is not read, so as to definitely detect a data written in the selected ferroelectric capacitor included in the memory cell block where the data is read.
In the first method for driving a semiconductor memory of this invention, the semiconductor memory contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof and a reading transistor whose gate is connected to one end of the plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a selected ferroelectric capacitor selected from the plurality of ferroelectric capacitors; a set line connected to the other end of the plurality of successively connected ferroelectric capacitors; a bit line connected to a drain of the reading transistor at one end thereof; a reset line connected to a source of the reading transistor at one end thereof; and a plurality of word lines respectively corresponding to the plurality of ferroelectric capacitors and provided perpendicularly to the bit line for selecting the selected ferroelectric capacitor, and voltages applied to the set line, the reset line and the word lines in selecting the selected ferroelectric capacitor or writing a data in the selected ferroelectric capacitor are a power voltage or a ground voltage.
In the first method for driving a semiconductor memory, the voltages applied to the set line, the reset line and the word lines in selecting a ferroelectric capacitor or in writing a data in the selected ferroelectric capacitor are the power voltage or the ground voltage. Therefore, there is no need to provide a negative voltage generator for reversing the displacement of the polarization of the ferroelectric film of the ferroelectric capacitor. Also, it is not necessary to make a potential applied to a first well region of the reading transistor in applying a reverse bias voltage between the upper electrode and the lower electrode differ from a potential applied to a second well region of the reading transistor different from the first well region. Therefore, there is no need to separate the well region of the reading transistor between the first and second well regions.
As a result, the area of the semiconductor memory can be reduced.
In the second method for driving a semiconductor memory of this invention, the semiconductor memory contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof and a reading transistor whose gate is connected to one end of the plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a selected ferroelectric capacitor selected from the plurality of ferroelectric capacitors; a set line connected to the other end of the plurality of successively connected ferroelectric capacitors; a bit line connected to a drain of the reading transistor at one end thereof; a reset line connected to a source of the reading transistor at one end thereof; and a plurality of word lines respectively corresponding to the plurality of ferroelectric capacitors and provided perpendicularly to the bit line for selecting the selected ferroelectric capacitor, and when none of the plurality of ferroelectric capacitors included in the memory cell block is selected in reading a data, the reading transistor included in the memory cell block is placed in an off-state.
In the second method for driving a semiconductor memory, when none of the plural ferroelectric capacitors included in the memory cell block is selected in reading a data, the reading transistor included in this memory cell block is placed in an off-state. Therefore, no current flows between the bit line and the reset line. Accordingly, in reading a data from a ferroelectric capacitor included in another memory cell block, even when a voltage is applied between the upper electrode and the lower electrode of the ferroelectric capacitor included in this memory cell block, this voltage application does not prevent the data read from a ferroelectric capacitor of another memory cell block.
Accordingly, the operation margin in reading a data can be enlarged, resulting in realizing a stable operation.
In the third method for driving a semiconductor memory of this invention, the semiconductor memory contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof and a reading transistor whose gate is connected to one end of the plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a selected ferroelectric capacitor selected from the plurality of ferroelectric capacitors; a set line connected to the other end of the plurality of successively connected ferroelectric capacitors; a bit line connected to a drain of the reading transistor at one end thereof; a reset line connected to a source of the reading transistor at one end thereof; and a plurality of word lines respectively corresponding to the plurality of ferroelectric capacitors and provided perpendicularly to the bit line for selecting the selected ferroelectric capacitor, and a step of writing a data in the selected ferroelectric capacitor includes sub-steps of causing a potential difference obtained by subtracting a ground voltage from a power voltage between an upper electrode and a lower electrode of the selected ferroelectric capacitor by applying the power voltage to the set line and applying the ground voltage to the reset line, whereby turning the polarization of the ferroelectric film of the selected ferroelectric capacitor to a direction of potential gradient of the potential difference; and after causing the potential difference, removing the potential difference caused between the upper electrode and the lower electrode of the selected ferroelectric capacitor by applying the ground voltage to the set line.
In the third method for driving a semiconductor memory, in writing a data in the selected ferroelectric capacitor, the data is written by causing a potential difference between the upper electrode and the lower electrode of the selected ferroelectric capacitor, and then, the potential difference caused between the upper electrode and the lower electrode of the selected ferroelectric capacitor is removed. Therefore, the lowering of the potential difference through a resistance component of the ferroelectric capacitor can be avoided, resulting in improving the retention characteristic.
In the fourth method for driving a semiconductor memory of this invention, the semiconductor memory contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof and a reading transistor whose gate is connected to one end of the plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a selected ferroelectric capacitor selected from the plurality of ferroelectric capacitors; a set line connected to the other end of the plurality of successively connected ferroelectric capacitors; a bit line connected to a drain of the reading transistor at one end thereof; a reset line connected to a source of the reading transistor at one end thereof; and a plurality of word lines respectively corresponding to the plurality of ferroelectric capacitors and provided perpendicularly to the bit line for selecting the selected ferroelectric capacitor, and a step of erasing a data written in the selected ferroelectric capacitor includes sub-steps of causing a potential difference obtained by subtracting a power voltage from a ground voltage between an upper electrode and a lower electrode of the selected ferroelectric capacitor by applying the ground voltage to the set line and applying the power voltage to the reset line, whereby turning the polarization of the ferroelectric film of the selected ferroelectric capacitor to a direction of potential gradient of the potential difference; and after causing the potential difference, removing the potential difference caused between the upper electrode and the lower electrode of the selected ferroelectric capacitor by applying the ground voltage to the reset line.
In the fourth method for driving a semiconductor memory, in erasing a data written in the selected ferroelectric capacitor, the data is erased by causing a potential difference reverse to that caused in writing the data between the upper electrode and the lower electrode of the selected ferroelectric capacitor, and then, the potential difference caused between the upper electrode and the lower electrode of the selected ferroelectric capacitor is removed. Therefore, the lowering of the potential difference through a resistance component of the ferroelectric capacitor can be avoided, resulting in improving the retention characteristic.
In the fifth method for driving a semiconductor memory of this invention, the semiconductor memory contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof and a reading transistor whose gate is connected to one end of the plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a selected ferroelectric capacitor selected from the plurality of ferroelectric capacitors; a set line connected to the other end of the plurality of successively connected ferroelectric capacitors; a bit line connected to a drain of the reading transistor at one end thereof; a reset line connected to a source of the reading transistor at one end thereof; and a plurality of word lines respectively corresponding to the plurality of ferroelectric capacitors and provided perpendicularly to the bit line for selecting the selected ferroelectric capacitor, and a step of reading a data from the selected ferroelectric capacitor includes sub-steps of applying a power voltage to the bit line and a ground voltage to the reset line, or applying the ground voltage to the bit line and the power voltage to the reset line, and detecting voltage change caused on the bit line by applying a reading voltage to the set line; and after detecting the voltage change, removing a potential difference caused between an upper electrode and a lower electrode of the selected ferroelectric capacitor by applying the ground voltage to the set line.
In the fifth method for driving a semiconductor memory, in reading a data from the selected ferroelectric capacitor, the data is read by applying the reading voltage to the set line, and then, the potential difference caused between the upper electrode and the lower electrode of the selected ferroelectric capacitor is removed. Therefore, the lowering of the potential difference through a resistance component of the ferroelectric capacitor can be avoided, resulting in improving the retention characteristic.
The fifth method for driving a semiconductor memory of this invention preferably further comprises, after the sub-step of removing the potential difference, a sub-step of turning off the reading transistor.
When the reading transistor is thus turned off after reading a data, no current flows between the bit line and the reset line. Therefore, similarly to the second method for driving a semiconductor memory, an operation for reading a data from a ferroelectric capacitor included in another memory cell block is not affected, so as to enlarge the operation margin in reading a data, resulting in realizing a stable operation.
In the sixth method for driving a semiconductor memory of this invention, the semiconductor memory contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof and a reading transistor whose gate is connected to one end of the plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a selected ferroelectric capacitor selected from the plurality of ferroelectric capacitors; a set line connected to the other end of the plurality of successively connected ferroelectric capacitors; a bit line connected to a drain of the reading transistor at one end thereof and to one end of a load resistance at the other end thereof; a reset line connected to a source of the reading transistor at one end thereof; and a plurality of word lines respectively corresponding to the plurality of ferroelectric capacitors and provided perpendicularly to the bit line for selecting the selected ferroelectric capacitor, and a step of reading a data from the selected ferroelectric capacitor includes sub-steps of applying a power voltage to the other end of the load resistance and a ground voltage to the reset line, or applying the ground voltage to the other end of the load resistance and the ground voltage to the reset line, and comparing, with a reference voltage, voltage change caused at both ends of the load resistance owing to a current flowing between the drain and the source of the reading transistor in applying a reading voltage to the set line; and after comparing the voltage change, removing a potential difference caused between an upper electrode and a lower electrode of the selected ferroelectric capacitor by applying the ground voltage to the set line.
In the sixth method for driving a semiconductor memory, in reading a data from the selected ferroelectric capacitor, the voltage change caused at both ends of the load resistance connected to the bit line in applying the reading voltage to the set line is compared with the reference voltage. Therefore, a data written in the selected ferroelectric capacitor can be definitely read. Also, after reading a data from the selected ferroelectric capacitor, the potential difference caused between the upper electrode and the lower electrode of the selected ferroelectric capacitor is removed, and hence, the lowering of the potential difference through a resistance component of the ferroelectric capacitor can be avoided, resulting in improving the retention characteristic.
The sixth method for driving a semiconductor memory of this invention preferably further comprises, after the sub-step of removing the potential difference, a sub-step of turning off the reading transistor.
When the reading transistor is thus turned off after reading a data, no current flows between the bit line and the reset line. Therefore, similarly to the second method for driving a semiconductor memory, an operation for reading a data from a ferroelectric capacitor included in another memory cell block is not affected, so as to enlarge the operation margin in reading a data, resulting in realizing a stable operation.
In the sixth method for driving a semiconductor memory, the semiconductor memory preferably further includes a second memory cell block having the same configuration as the memory cell block and disposed on a side of the memory cell block along a word line direction; and a second bit line connected, at one end thereof, to a drain of a second reading transistor included in the second memory cell block and connected, at the other end thereof, to one end of a second load resistance, and it is preferred that the set line is connected to the other end of a plurality of ferroelectric capacitors included in the second memory cell block, that the reset line is connected to a source of the second reading transistor included in the second memory cell block, and that the reference voltage corresponds to voltage change caused at both ends of the second load resistance owing to a current flowing between the drain and the source of the second reading transistor in applying the power voltage to the other end of the second load resistance and the ground voltage to the reset line, or applying the ground voltage to the other end of the second load resistance and the ground voltage to the reset line, and applying the reading voltage to the set line.
In this manner, the first voltage change caused at both ends of the former load resistance owing to a current flowing between the drain and the source of the reading transistor included in the memory cell block where a data is read is compared with the second voltage change caused at both ends of the latter load resistance owing to a current flowing between the drain and the source of the second reading transistor included in the second memory cell block where a data is not read. Thus, a data written in the selected ferroelectric capacitor included in the memory cell block where the data is read can be definitely detected.